Hardware Reference
In-Depth Information
The PLX Technology bus slave controller contains a standard configuration
space header (type 00H). This header contains the following data:
Offset
Register name
Description
Value
00-01H
Vendor identification
PCI device manufacturer ID
10B5H (PLX Technology)
02-03H
Device identification
PCI device ID
9050H
18-1BH
Base address register
I/O base address of card
0000xxxx
2C-2DH
Subsystem Vendor ID
Board manufacturer ID
12ABH (Arcom)
2E-2FH
Subsystem ID
Board ID
0605H (APCI-ADADIO)
3CH
Interrupt line
Interrupt line assigned to device
0x
The above registers are accessed using PCI BIOS functions.
The
APCI-ADADIO
uses
an
indexed
addressing
scheme
to
access
the
on-board devices and special function registers.
The addressing scheme is
described in the following table:
I/O address
Function
Direction
Base
Index register
Write
Base
+
1
Control/Status
Read/Write
Base
+
2
ADC/DAC LSB data
Read/Write
Base
+
3
ADC/DAC MSB data
Read/Write
The APCI-ADADIO contains a single 12-bit successive approximation
analogue-to-digital converter. The input to this device is connected to an 8-way
multiplexer (APCI-ADADIOCD) or 16-way multiplexer (APCI-ADADIOCS).
Prior to an analogue-to-digital conversion the appropriate channel can be
selected by writing to the multiplexer channel select register. The ADC may be
triggered by three different sources which are selected by links. These sources
can be:
1
Software trigger, initiated by an I/O write sequence.
2
Hardware trigger from an external TTL input (approximately 1-2
µ
slow
pulse).
3
Periodic timer programmed from the on-board counter/timer Channel 0.
The
following
sequence
can
be
used
to
perform
an
analogue-to-digital
conversion when using the software trigger mode:
1
Write 01H to the Base address
2
Write the appropriate multiplexer channel value to Base+1
3
Wait for approximately 50
µ
s for the input to settle
4
Write 00H to the Base address
