PC expansion bus systems - PC Based Instrumentation and Control - page 97

Each of the eight inputs is optically isolated and fed via a bridge recti-
fier arrangement which allows for either AC or DC inputs of between 5 and
28 V. A fixed, current limiting, resistor of 1.6 k is fitted to each input. The
optoisolators provide electrical isolation of up to 500 V (channel-channel and
channel-ground). A simplified block schematic for the PDISO-8 is shown in
Figure 2.25.
The response time of each input may be individually selected using software
control (the earlier ISA version of this card used dual-in-line switches to select
the input filters). Input response time is typically 20 µ s without the filter and
5 ms when the filter is switched in (note that filters are normally required with
AC inputs in order to avoid the digital input pulsing on and off at twice the AC
input frequency!).
The eight relay outputs each have contacts rated at 3 A at 120 V AC or 28 V
DC (resistive loads). The maximum contact resistance is 100 m and both
SPDT (Channels 0 to 4) and SPST (Channels 5 to 7) contacts are available.
Relay operating time is 20 ms (max.) and release time 10 ms (max.).
The PDISO-8 uses only the + 5 V power rail from the PC and requires a
typical supply current of 1 A (all relays energized). The I/O lines from the
board connect via a standard 37-pin D-type male connector fitted to the rear
metal bracket. The I/O connector pin assignment is shown in Figure 2.26.
The board address is selected by means of a dual-in-line switch. The PDISO-8
board occupies four consecutive addresses in the PC I/O address space of which
only two addresses are actually used. The base address is selected by means of
the dual-in-line switch and the two registers are located at (base address) and
(base address + 1). The I/O map for the board is as follows:

I/O address Function Mode

Base address Relay outputs Read/write

Base address + 1 Isolated inputs Read only

Figure 2.26 Connector pin
assignment for the PDISO-8

Each bit in the appropriate register corresponds to the equivalent I/O channel
number. Bits are therefore allocated as follows:

Data bit

Address D7 D6 D5 D4 D3 D2 D1 D0

Base OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Base + 1 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

As an example, assuming that the base address has been set to 300 hexadec-
imal, the relays can be operated by writing data to 0300H while the inputs can
be sensed by reading data from 0301H. In the former case, a set bit (logic 1)
will energize the relay connected to the channel in question while in the latter
case, a set bit (logic 1) will indicate that an input has been asserted.
The state of the output register can be read by appropriate software in order to
ascertain the current state of the relays. In some applications this can be useful
since it avoids the need to preserve the state of the relay port within a variable.
In order to operate a particular relay without disturbing any of the others, it is