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(a) Generalized modular multiplier (GM)
(b) AOP modular multiplier (AM)
Fig. 1. Modular multiplier
Table 1. Comparison for modular multipliers
Item
Function Number
of cells
Latency
Hardware
Complexity
Critical
Path
Circuit
Chaudhury in
[3]
AB+C
m
m
2 m AND
2 m XOR
4m REG
AND+XOR
Kim in [5]
AB
m +1
2 m +1
( m +1) AND
m XOR
2( m +1) REG
AND
+XOR(log 2 m )
AB+C
m
m
GM
2 m AND
2 m XOR
3 m REG
AND
+2 XOR
AM
AB+C
m +1
+1
m +1 AND
m +1 XOR
2( m +1) REG
AND+XOR
References
1. Reed, I. S. and Truong, T. K.: The use of finite fields to compute convolutions. IEEE Trans.
on Information Theory , IT-21 (Mar. 1975) 208-213
2. Neumann, V.: The theory of self-reproducing automata , Univ. of Illinois Press, Urbana
&
London (1966)
3. Choudhury, P. Pal. and Barua, R.: Cellular Automata Based VLSI Architecture for Comput-
ing Multiplication and Inverses in GF(2 m ). IEEE 7 th International Conference on VLSI De-
sign , Jan. (1994)
4. Itoh, T. and Tsujii, S.: Structure of parallel multipliers for a class of finite fields GF(2 m ).
Info. Comp ., vol. 83 (1989) 21-40
5. Kim, H. S.: Bit-Serial AOP Arithmetic Architecture for Modular Exponentiation , Ph. D.
Thesis, Kyungpook National Univ. (2002)
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