Information Technology Reference
In-Depth Information
Table 2.
ASIC (0.33um) Synthesis Results
Encryption
Algorithms
CIKS-1 Cipher
SPECTR-H64
Covered Area
Covered Area
F
(GHz)
F
(GHz)
Components
# Gates
Area
# Gates
Area
6
3 sqmil
6
3 sqmil
I) P
2/1
2.12
2.12
24
12 sqmil
1.16
24
12 sqmil
1.16
II) P
4/4
72
36 sqmil
0.71
72
36 sqmil
0.71
III) P
8/12
192
96 sqmil
0.53
-
-
-
IV) P
16/32
288
144 sqmil
0.73
-
-
-
V) P
32/48
480
240 sqmil
0.87
480
240 sqmil
0.87
VI) P
32/80
Using the results presented in Tables 1 and 2 it is easy to estimate the implementa-
tion cost of the P
n/m
-boxes of different orders for
n =
2
k
. Indeed, the cost correspond-
ing to implementation of one layer of the P
2/1
boxes is
w
1
=
w
0
n
/2 and for the
s
-layer
P
n/m
-box of the
h
th order one can estimate the cost as
w
s
=
w
0
ns
/2 = (
w
0
n
log
2
nh
)/2,
where
w
0
is the implementation cost of the box P
2/1
and
h
= 1, 2, 4, …,
n
/4.
For the presented allocated resources, the equivalent number of CLBs and gates
has been used, for the FPGA and the ASIC devices respectively. It is obvious that the
allocated area is increasing with an exponential function for larger boxes, but still
remains in low levels for all the CP boxes. For example and in order to have a better
overview of the covered area resources, it is mentioned that one bit adder is imple-
mented by 5 gates. A 32-bit serial full adder needs 160 gates in order to be integrated.
The operating frequency for each CP box has almost the same value for both FPGA
and ASIC implementations and it is very high.
3
SPECTR-H64 and CIKS-1 Hardware Implementations
Hardware implementations of both proposed ciphers are designed and coded in
VHDL hardware description language. Both CIKS-1 and SPECTR-H64 were imple-
mented using two complete different implementation hardware modules: Application
Specific Integrated Circuit (ASIC) and Field Programmable Gate Arrays (FPGA).
The performance characteristics of both ASICs and FPGAs are substantially different
compared with a general-purpose microprocessor. ASICs and FPGAs have the advan-
tage that can use all the resources for pipelining data transformation, or parallel proc-
essing. On the other hand, the internal structure of the microprocessors functional
units limits the parallel processing and pipelining transformation. In addition the
