Digital Signal Processing Reference
In-Depth Information
moved to the end of the evaluation process to help eliminate overflows. The
digital filter design references in Appendix A provide further information on other
structures than the quadratic form, including those for representing poles located
extremely close to the unit circle. Antoniou's, Oppenheim/Shafer's (1975), and
Proakis/Manolakis's texts provide valuable and detailed material.
Several other points can be made when discussing the coefficients and
internal processing of the filter calculations. In both FIR and IIR filter
implementation, the final output values are stored in a register that gradually
accumulates the value of the final output. This accumulator should normally be
allocated as many bits of representation as possible because it controls the ultimate
accuracy of the processor. Overflow and underflow are potential problems for the
accumulator since it is hard to predict the exact nature of incoming signals. Most
present dedicated DSP chips provide some form of scaling that can be applied to
the input so that temporary large variations can be accommodated without
incurring a great deal of error. This scaling bit can effectively be used as a
temporary additional bit of accuracy for accumulated values to prevent overflow.
However, if overflow is inevitable, it is better to have a processor that will simply
saturate at its maximum level than to allow an overflow that can be interpreted as
a swing from positive to negative value.
In recursive systems that use finite precision representations, a troublesome
problem called limit cycle oscillation can occur. There are actually two types of
limit cycles: overflow and quantization. Overflow limit cycles (also called large-
signal limit cycles) are due to the unmanaged overflow of the accumulator during
processing. Most overflow limit cycles can be effectively eliminated by the proper
use of signal scaling at the input of the system and saturation arithmetic in the
accumulator. Many DSP processors include some scaling feature within the
processor unit that allows the input signal to be reduced in size. However, a
reduction in the size of the input signal also reduces the SNR of the system,
although this is usually better than the distortion produced by an overflow.
Another useful feature on many DSP systems today is the use of saturation
arithmetic within the processing unit. This feature will saturate the value to its
positive or negative limit rather than overflow the accumulator. Again, this will
result in distortion, but usually less than the overflow would produce. Of course,
another way to help control overflow limit cycles is to increase the size of the
accumulator, if the processing system allows the accumulator to be larger than the
standard coefficient storage size.
The quantization limit cycles (also called small-signal limit cycles) generally
result from the handling of quantization within the system and are noticeable when
the output should be constant or zero. This problem is the result of the input signal
changes being less than the quantization level. Two methods have been developed
to combat this type of limit cycle. The first, which may not be a practical
alternative, is to increase the number of bits assigned to the representation of the
signal values in order to reduce the quantization error. By reducing the
quantization error, the limit cycles can either be eliminated altogether, or reduced
to a tolerable level. The second method suggests that the products produced by
