Image Processing Reference
In-Depth Information
analysis. During this early phase of the development this analysis was insightful and in cooperation
with a number of detailed project meetings and code reviews lead to an overall improvement of the
development process.
Memory profiling on every integration build was integrated into the toolflow as the next step
(see Figure .). Subsequently testing became more fine-grained with very specific questions on
the roadmap, e.g., the influence of topology variations or excessive clustering of nodes on the net-
working performance. Sensitivity analysis was performed using specific parametrized versions of the
software that was tested in individual test jobs with similar characteristics, e.g., day, fixed number
of nodes. For a detailed power/performance analysis, a combined setup of four nodes attached to the
instrumentation setup described in Section .. with two nodes inside the TCT chamber and two
nodes outside as well as one node additionally attached to a precision counter for monitoring the
stability of the system clock over longer periods of time was used. A basic current and voltage profile
with the characteristics of the time division multiple access (TDMA) communication scheme of the
PermaSense protocol can be seen in Figure .. It can be seen that basically the protocol performs as
expected with the four nodes in sync. Only occasionally a node in the TCT chamber needs to resync
(longer active phase seen in period , , and ) due to the influence of the cooling. A detailed view
on one of the communication rounds is shown in Figure .. Here the effect of high power load on
an already drained battery can be seen when load increases in the active phase of the protocol. With
a lower operating limit of . V as given for the TinyNode, it is clear that we are already reaching a
case of possible malfunction of the system here although the battery seems to be still healthy when
the node is sleeping. Taking a closer look at the current consumption in sleep mode by zooming
in on the current traces taken (see Figure .) reveals considerable differences on the four nodes
under test. Clearly there are device variations and spurious errors visible, but it seems as if there are
also systematic errors (the lowest curve shows repetitive, unstable behavior). Even worse, this (mis-)
behavior has been observed on different nodes, but it could not be observed on all nodes! To date we
have not been able to find out all details of what is happening here, but the analysis has sharpened our
TinyOS memory usage
45,000
40,000
35,000
30,000
25,000
20,000
15,000
10,000
5,000
0
28/07
04/08
11/08
18/08
25/08
01/09
date
08/09
15/09
22/09
29/09
06/10
Ram
Flash
Stack
Ram usage
Flash usage
Stack usage
45,000
70
60
50
40
30
20
10
40,000
35,000
30,000
25,000
6,000
5,000
4,000
3,000
2,000
1,000
0
20,000
15,000
10,000
5,000
0
0
01/09
Date
Flash
01/10
30/07
14/08
29/08
Date
Ram
13/09
28/09
01/08
30/07
14/08
29/08
13/09
28/09
Date
Stack
FIGURE .
Evolution of memory usage over three months of the development process.
