Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 70

2
Memory Hierarchy Design
Ideally one would desire an indefinitely large memory capacity such that any particular … word
would be immediately available. … We are … forced to recognize the possibility of constructing a
hierarchy of memories, each of which has greater capacity than the preceding but which is less
quickly accessible.
A. W. Burks, H. H. Goldstine, and J. von Neumann
Preliminary Discussion of the Logical Design of an Electronic Computing Instrument (1946)
2.1 Introduction
2.2 Ten Advanced Optimizations of Cache Performance
2.3 Memory Technology and Optimizations
2.4 Protection: Virtual Memory and Virtual Machines
2.5 Crosscutting Issues: The Design of Memory Hierarchies
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-A8 and Intel Core i7
2.7 Fallacies and Pitfalls
2.8 Concluding Remarks: Looking Ahead
2.9 Historical Perspective and References
Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li
2.1 Introduction
Computer pioneers correctly predicted that programmers would want unlimited amounts of
fast memory. An economical solution to that desire is a memory hierarchy , which takes advant-
age of locality and trade-offs in the cost-performance of memory technologies. The principle of
locality , presented in the first chapter, says that most programs do not access all code or data
uniformly. Locality occurs in time ( temporal locality ) and in space ( spatial locality ). This principle,
plus the guideline that for a given implementation technology and power budget smaller hard-
ware can be made faster, led to hierarchies based on memories of different speeds and sizes.
Figure 2.1 shows a multilevel memory hierarchy, including typical sizes and speeds of access.