References - Computer Architecture: A Quantitative Approach - page 719

Hall; 1984; (Although out of print, it is available online at www.cs.washington.edu/homes/
lazowska/qsp/ .).
358. Lebeck AR, Wood DA. Cache profiling and the SPEC benchmarks: A case study. Computer .
1994;27(10):15-26 (October).
359. Lee R. Precision architecture. Computer . 1989;22(1):78-91 (January).
360. Lee WV, et al. Debunking the 100X GPU vs CPU myth: An evaluation of throughput com-
puting on CPU and GPU. Proc 37th Annual Int'l Symposium on Computer Architecture (ISCA)
2010.
361. Leighton FT. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hyper-
cubes San Francisco: Morgan Kaufmann; 1992.
362. Leiner AL. System specifications for the DYSEAC. J ACM . 1954;1(2):57-81 (April).
363. Leiner AL, Alexander SN. System organization of the DYSEAC. IRE Trans of Electronic Com-
puters . 1954;EC-3(1):1-10 (March).
364. Leiserson CE. Fat trees: Universal networks for hardware-efficient supercomputing. IEEE
Trans on Computers . 1985;C-34(10):892-901 (October).
365. Lenoski D, Laudon J, Gharachorloo K, Gupta A, Hennessy JL. The Stanford DASH multi-
processor. Proc 17th Annual Int'l Symposium on Computer Architecture (ISCA) 1990;148-159.
366. Lenoski D, Laudon J, Gharachorloo K, et al. The Stanford DASH multiprocessor. IEEE Com-
puter . 1992;25(3):63-79 (March).
367. Levy H, Eckhouse R. Computer Programming and Architecture: The VAX Boston: Digital
Press; 1989.
368. Li K. IVY: A shared virtual memory system for parallel computing . Proc 1988 Int'l Conf on Par-
allel Processing University Park, Penn: Pennsylvania State University Press; 1988.
369. Li, S., K. Chen, J. B. Brockman, N. Jouppi [2011]. “Performance Impacts of Non-blocking
Caches in Out-of-order Processors,” HP Labs Tech Report HPL-2011-65 (full text available
at htp://Library.hp.com/techpubs/2011/Hpl-2011-65.html ).
370. Lim K, Ranganathan P, Chang J, Patel C, Mudge T, Reinhardt S. Understanding and design-
ing new system architectures for emerging warehouse-computing environments. Proc 35th
Annual Int'l Symposium on Computer Architecture (ISCA) 2008.
371. Lincoln NR. Technology and design trade offs in the creation of a modern supercomputer.
IEEE Trans on Computers . 1982;C-31(5):363-376 (May).
372. Lindholm T, Yellin F. The Java Virtual Machine Specification 2nd ed. Reading, Mass:
Addison-Wesley; 1999; (also available online at java.sun.com/docs/books/vmspec/ ).
373. Lipasti MH, Shen JP. Exceeding the dataflow limit via value prediction. Proc 29th Int'l Sym-
posium on Microarchitecture 1996.
374. Lipasti MH, Wilkerson CB, Shen JP. Value locality and load value prediction. Proc Seventh
Conf on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
1996;138-147.
375. Liptay JS. Structural aspects of the System/360 Model 85, Part II: The cache. IBM Systems J.
1968;7(1):15-21.
376. Lo J, Barroso L, Eggers S, Gharachorloo K, Levy H, Parekh S. An analysis of database work-
load performance on simultaneous multithreaded processors. Proc 25th Annual Int'l Sym-
posium on Computer Architecture (ISCA) 1998;39-50.
377. Lo J, Eggers S, Emer J, Levy H, Stamm R, Tullsen D. Converting thread-level parallelism in-
to instruction-level parallelism via simultaneous multithreading. ACM Trans on Computer
Systems . 1997;15(2):322-354 (August).
378. Lovet T, Thakkar S. The Symmetry multiprocessor system. Proc 1988 Int'l Conf of Parallel
Processing 1988;303-310.