References - Computer Architecture: A Quantitative Approach - page 714

241. Gray J, van Ingen C. Empirical Measurements of Disk Failure Rates and Error Rates Red-
mond, Wash: MSR-TR-2005-166, Microsoft Research; 2005.
242. Greenberg A, Jain N, Kandula S, et al. VL2: A Scalable and Flexible Data Center Network.
In: Proc ACM SIGCOMM . 2009.
243. Grice C, Kanellos M. Cell phone industry at crossroads: Go high or low? . CNET News 2000;
August 31 technews.netscape.com/news/0-1004-201-2518386-0.html?tag=st.ne.1002.tgif.sf ; 2000.
244. Groe JB, Larson LE. CDMA Mobile Radio Design Boston: Artech House; 2000.
245. Gunther KD. Prevention of deadlocks in packet-switched data transport systems. IEEE
Trans on Communications . 1981;COM-29(4):512-524 (April).
246. Hagersten E, Koster M. WildFire: A scalable path for SMPs. Proc Fifth Int'l Symposium on
High-Performance Computer Architecture 1998.
247. Hagersten E, Landin A, Haridi S. DDM—a cache-only memory architecture. IEEE Com-
puter . 1992;25(9):44-54 (September).
248. Hamacher VC, Vranesic ZG, Zaky SG. Computer Organization 2nd ed. New York:
McGraw-Hill; 1984.
249. Hamilton J. [2009]. “Data center networks are in my way,” paper presented at the Stanford
Clean Slate CTO Summit, October 23, 2009 ( htp://mvdirona.com/jrh/TalksAndPapers/
JamesHamilton_CleanSlateCTO2009.pdf ) .
250. Hamilton J. [2010]. “Cloud computing economies of scale,” paper presented at the AWS
Workshop on Genomics and Cloud Computing, June 8, 2010, Seatle, Wash. ( ht-
tp://mvdirona.com/jrh/TalksAndPapers/JamesHamilton_GenomicsCloud20100608.pdf ).
251. Handy J. The Cache Memory Book Boston: Academic Press; 1993.
252. Hauck EA, Dent BA. Burroughs' B6500/B7500 stack mechanism. Proc AFIPS Spring Joint
Computer Conf. 1968;245-251.
253. Heald R, Aingaran K, Amir C, et al. Implementation of third-generation SPARC V9 64-b
microprocessor. ISSCC Digest of Technical Papers 2000;412-413 and slide supplement.
254. Heinrich J. MIPS R4000 User's Manual Englewood Cliffs, N.J.: Prentice Hall; 1993.
255. Henly, M., and B. McNut [1989]. DASD I/O Characteristics: A Comparison of MVS to VM ,”
Tech. Rep. TR 02.1550 (May), IBM General Products Division, San Jose, Calif.
256. Hennessy J. VLSI processor architecture. IEEE Trans on Computers . 1984;C-33(11):1221-1246
(December).
257. Hennessy J. VLSI RISC processors. VLSI Systems Design . 1985;6(10):22-32 (October).
258. Hennessy J, Jouppi N, Basket F, Gill J. MIPS: A VLSI processor architecture. In: CMU Con-
ference on VLSI Systems and Computations . Rockville, Md.: Computer Science Press; 1981.
259. Hewlet-Packard. PA-RISC 2.0 Architecture Reference Manual 3rd ed. Palo Alto, Calif:
Hewlet-Packard; 1994.
260. Hewlet-Packard. HP's '5NINES:5MINUTES' Vision Extends Leadership and Redefines High
Availability

in Mission-Critical Environments . February 10

www.future.enterprisecomputing.hp.com/ia64/news/5nines_vision_pr.html ; 1998.
261. Hill, M. D. [1987]. “Aspects of Cache Memory and Instruction Buffer Performance,” Ph.D.
thesis, Tech. Rep. UCB/CSD 87/381, Computer Science Division, University of California,
Berkeley.
262. Hill MD. A case for direct mapped caches. Computer . 1988;21(12):25-40 (December).
263. Hill MD. Multiprocessors should support simple memory consistency models. IEEE Com-
puter . 1998;31(8):28-34 (August).
264. Hillis WD. The Connection Multiprocessor Cambridge, Mass: MIT Press; 1985.
265. Hillis WD, Steele GL. Data parallel algorithms . Communications of the ACM .

1986;29(12):1170-1183 (December) htp://doi.acm.org/10.1145/7902.7903 ; 1986.