Hardware Reference
In-Depth Information
174. Duato J, Lysne O, Pang R, Pinkston TM. Part I: A theory for deadlock-free dynamic re-
coniguration of interconnection networks. IEEE Trans on Parallel and Distributed Systems .
2005b;16(5):412-427 (May).
175. Dubois M, Scheurich C, Briggs F. Synchronization, coherence, and event ordering. IEEE
Computer . 1988;21(2):9-21 (February).
176. Dunigan W, Veter K, White K, Worley P. Performance evaluation of the Cray X1 distrib-
uted shared memory architecture. IEEE Micro 2005;30-40 January/February.
177. Eden A, Mudge T. The YAGS branch prediction scheme. Proc of the 31st Annual ACM/IEEE
Int'l Symposium on Microarchitecture 1998;69-80.
178. Edmondson JH, Rubinfield PI, Preston R, Rajagopalan V. Superscalar instruction execution
in the 21164 Alpha microprocessor. IEEE Micro . 1995;15(2):33-43.
179. Eggers, S. [1989]. “Simulation Analysis of Data Sharing in Shared Memory Multipro-
cessors,” Ph.D. thesis, University of California, Berkeley.
180. Elder J, Gotlieb A, Kruskal CK, et al. Issues related to MIMD shared-memory computers:
The NYU Ultracomputer approach. Proc 12th Annual Int'l Symposium on Computer Architec-
ture (ISCA) 1985;126-135.
181. Ellis JR. Bulldog: A Compiler for VLIW Architectures Cambridge, Mass: MIT Press; 1986.
182. Emer JS, Clark DW. A characterization of processor performance in the VAX-11/780. Proc
11th Annual Int'l Symposium on Computer Architecture (ISCA) 1984;301-310.
183. Enriquez P. What happened to my dial tone? A study of FCC service disruption reports.
poster, Richard Tapia Symposium on the Celebration of Diversity in Computing 2001.
184. Erlichson A, Nuckolls N, Chesson G, Hennessy JL. SoftFLASH: Analyzing the performance
of clustered distributed virtual shared memory. Proc Seventh Int'l Conf on Architectural Sup-
port for Programming Languages and Operating Systems (ASPLOS) 1996;210-220.
185. Esmaeilzadeh H, Cao T, Xi Y, Blackburn SM, McKinley KS. Looking Back on the Language
and Hardware Revolution: Measured Power, Performance, and Scaling. Proc 16th Int'l Conf
on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2011.
186. Evers M, Patel SJ, Chappell RS, Pat YN. An analysis of correlation and predictability: What
makes two-level branch predictors work. Proc 25th Annual Int'l Symposium on Computer Ar-
chitecture (ISCA) 1998;52-61.
187. Fabry RS. Capability based addressing. Communications of the ACM . 1974;17(7):403-412
(July).
188. Falsafi B, Wood DA. Reactive NUMA: A design for unifying S-COMA and CC-NUMA.
Proc 24th Annual Int'l Symposium on Computer Architecture (ISCA) 1997;229-240.
189. Fan X, Weber W, Barroso LA. Power provisioning for a warehouse-sized computer. Proc
34th Annual Int'l Symposium on Computer Architecture (ISCA) 2007.
190. Farkas KI, Jouppi NP. Complexity/performance trade-offs with non-blocking loads. Proc
21st Annual Int'l Symposium on Computer Architecture (ISCA) 1994.
191. Farkas KI, Jouppi NP, Chow P. How useful are non-blocking loads, stream buffers and
speculative execution in multiple issue processors? Proc First IEEE Symposium on High-Per-
formance Computer Architecture 1995;78-89.
192. Farkas KI, Chow P, Jouppi NP, Vranesic Z. Memory-system design considerations for
dynamically-scheduled processors. Proc 24th Annual Int'l Symposium on Computer Architec-
ture (ISCA) 1997;133-143.
193. Fazio D. It's really much more fun building a supercomputer than it is simply inventing
one. Proc IEEE COMPCON 1987;102-105.
194. Fisher JA. Trace scheduling: A technique for global microcode compaction. IEEE Trans on
Computers . 1981;30(7):478-490 (July).
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