Hardware Reference
In-Depth Information
87. Brandt M, Brooks J, Cahir M, Hewit T, Lopez-Pineda E, Sandness D. The Benchmarker's
Guide for Cray SV1 Systems Seatle, Wash: Cray Inc.; 2000.
88. Brent RP, Kung HT. A regular layout for parallel adders. IEEE Trans on Computers .
1982;C-31:260-264.
89. Brewer EA, Kuszmaul BC. How to get good performance from the CM-5 data network.
Proc Eighth Int'l Parallel Processing Symposium 1994.
90. Brin S, Page L. The anatomy of a large-scale hypertextual Web search engine. Proc 7th Int'l
World Wide Web Conf. 1998;107-117.
91. Brown A, Paterson DA. Towards maintainability, availability, and growth benchmarks: A
case study of software RAID systems. Proc 2000 USENIX Annual Technical Conf. 2000.
92. Bucher IV, Hayes AH. I/O performance measurement on Cray-1 and CDC 7000 computers.
Proc Computer Performance Evaluation Users Group, 16th Meeting 1980;245-254.
93. Bucher IY. The computational speed of supercomputers. Proc Int'l Conf on Measuring and
Modeling of Computer Systems (SIGMETRICS 1983) 1983;151-165.
94. Bucholz W. Planning a Computer System: Project Stretch New York: McGraw-Hill; 1962.
95. Burgess N, Williams T. Choices of operand truncation in the SRT division algorithm. IEEE
Trans on Computers . 1995;44(7):933-938.
96. Burkhardt III, H., S. Frank, B. Knobe, J. Rothnie [1992]. Overview of the KSR1 Computer Sys-
tem , Tech. Rep. KSR-TR-9202001, Kendall Square Research, Boston, Mass.
97. Burks AW, Goldstine HH, von Neumann J. Preliminary discussion of the logical design of
an electronic computing instrument. In: Aspray W, Burks A, eds. Report to the U.S Army
Ordnance Department, p 1; . Los Angeles, Calif.: MIT Press, Cambridge, Mass., and Tomash
Publishers; 1987;97-146. also appears in Papers of John von Neumann .
98. Calder B, Reinman G, Tullsen DM. Selective value prediction. Proc 26th Annual Int'l Sym-
posium on Computer Architecture (ISCA) 1999.
99. Calder B, Grunwald D, Jones M, et al. Evidence-based static branch prediction using ma-
chine learning. ACM Trans Program Lang Syst. 1997;19(1):188-222.
100. Callahan D, Dongarra J, Levine D. Vectorizing compilers: A test suite and results. Proc
ACM/IEEE Conf on Supercomputing 1988;98-105.
101. Cantin JF, Hill MD. Cache Performance for Selected SPEC CPU2000 Benchmarks . www.jfred.org/
cache-data.html ; 2001; (June).
102. Cantin JF, Hill MD. Cache Performance for SPEC CPU2000 Benchmarks, Version 3.0. In:
www.cs.wisc.edu/multifacet/misc/spec2000cache-data/index.html ; 2003.
103. Carles S. Amazon reports record Xmas season, top game picks . Gamasutra, December 27 ht-
tp://www.gamasutra.com/php-bin/news_index.php?story=7630 ; 2005.
104. Carter J, Rajamani K. Designing energy-efficient servers and data centers. IEEE Computer .
2010;43(7):76-78 (July).
105. Case RP, Padegs A. The architecture of the IBM System/370. Communications of the ACM .
1978;21(1):73-96 Also appears in.
105. Siewiorek DP, Bell CG, Newell A. Computer Structures: Principles and Examples New
York: McGraw-Hill; 1978; 830-855.
106. Censier L, Feautrier P. A new solution to coherence problems in multicache systems. IEEE
Trans on Computers . 1978;C-27(12):1112-1118 (December).
107. Chandra R, Devine S, Verghese B, Gupta A, Rosenblum M. Scheduling and page migration
for multiprocessor compute servers. Sixth Int'l Conf on Architectural Support for Programming
Languages and Operating Systems (ASPLOS) 1994;12-24.
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