Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 702

ing instruction until the writing instruction finishes—just the opposite. For example, con-
sider the sequence:
MUL.D F0,F6,F4
DSUB.D F8,F0,F2
ADD.D F2,F10,F2
The DSUB.D depends on the MUL.D (a RAW hazard), thus the MUL.D must be allowed to complete
before the DSUB.D . If the MUL.D were stalled for the DSUB.D due to the inability to distinguish
between RAW and WAR hazards, the processor will deadlock. This sequence contains a
WAR hazard between the ADD.D and the DSUB.D , and the ADD.D cannot be allowed to com-
plete until the DSUB.D begins execution. The difficulty lies in distinguishing the RAW hazard
between MUL.D and DSUB.D , and the WAR hazard between the DSUB.D and ADD.D . To see just why
the three-instruction scenario is important, trace the handling of each instruction stage by
stage through issue, read operands, execute, and write result. Assume that each scoreboard
stage other than execute takes 1 clock cycle. Assume that the MUL.D instruction requires 3
clock cycles to execute and that the DSUB.D and ADD.D instructions each take 1 cycle to execute.
Finally, assume that the processor has two multiply function units and two add function
units. Present the trace as follows.
1. Make a table with the column headings Instruction, Issue, Read Operands, Execute,
Write Result, and Comment. In the first column, list the instructions in program order
(be generous with space between instructions; larger table cells will beter hold the
results of your analysis). Start the table by writing a 1 in the Issue column of the MUL.D
instruction row to show that MUL.D completes the issue stage in clock cycle 1. Now, fill
in the stage columns of the table through the cycle at which the scoreboard first stalls
an instruction.
2. For a stalled instruction write the words “waiting at clock cycle X,” where X is the
number of the current clock cycle, in the appropriate table column to show that the
scoreboard is resolving an RAW or WAR hazard by stalling that stage. In the Com-
ment column, state what type of hazard and what dependent instruction is causing
the wait.
3. Adding the words “completes with clock cycle Y” to a “waiting” table entry, fill in the
rest of the table through the time when all instructions are complete. For an instruction
that stalled, add a description in the Comments column telling why the wait ended
when it did and how deadlock was avoided. (Hint: Think about how WAW hazar-
ds are prevented and what this implies about active instruction sequences.) Note the
completion order of the three instructions as compared to their program order.
C.14 [10/10/10] <C.5> For this problem, you will create a series of small snippets that illustrate
the issues that arise when using functional units with different latencies. For each one,
draw a timing diagram similar to Figure C.38 that illustrates each concept, and clearly in-
dicate the problem.
a. [10] <C.5> Demonstrate, using code different from that used in Figure C.38 , the struc-
tural hazard of having the hardware for only one MEM and WB stage.
b. [10] <C.5> Demonstrate a WAW hazard requiring a stall.