Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 699

The first ALU stage is used for effective address calculation for memory references and
branches. The second ALU cycle is used for operations and branch comparison. RF is both a
decode and register-fetch cycle. Assume that when a register read and a register write of the
same register occur in the same clock the write data are forwarded.
a. [12] <C.2> Find the number of adders needed, counting any adder or incrementer;
show a combination of instructions and pipe stages that justify this answer. You need
only give one combination that maximizes the adder count.
b. [13] <C.2> Find the number of register read and write ports and memory read and
write ports required. Show that your answer is correct by showing a combination of
instructions and pipeline stage indicating the instruction and the number of read ports
and write ports required for that instruction.
c. [20] <C.3> Determine any data forwarding for any ALUs that will be needed. Assume
that there are separate ALUs for the ALU1 and ALU2 pipe stages. Put in all forward-
ing among ALUs necessary to avoid or reduce stalls. Show the relationship between
the two instructions involved in forwarding using the format of the table in Figure
C.26 but ignoring the last two columns. Be careful to consider forwarding across an
intervening instruction—for example,
ADD R1, ...
any instruction
ADD ..., R1, ...
d. [20] <C.3> Show all of the data forwarding requirements necessary to avoid or reduce
stalls when either the source or destination unit is not an ALU. Use the same format
as in Figure C.26 , again ignoring the last two columns. Remember to forward to and
from memory references.
(i.e., [15] <C.3> Show all the remaining hazards that involve at least one unit other than an
ALU as the source or destination unit. Use a table like that shown in Figure C.25 , but
replace the last column with the lengths of the hazards.
f. [15] <C.2> Show all control hazards by example and state the length of the stall. Use a
format like that shown in Figure C.11 , labeling each example.
C.6 [12/13/13/15/15] <C.1, C.2, C.3> We will now add support for register-memory ALU op-
erations to the classic five-stage RISC pipeline. To offset this increase in complexity, all
memory addressing will be restricted to register indirect (i.e., all addresses are simply a
value held in a register; no offset or displacement may be added to the register value). For
example, the register-memory instruction ADD R4, R5, (R1) means add the contents of re-
gister R5 to the contents of the memory location with address equal to the value in register
R1 and put the sum in register R4. Register-register ALU operations are unchanged. The
following items apply to the integer RISC pipeline: