Hardware Reference
In-Depth Information
1. Issue —If a functional unit for the instruction is free and no other active instruction has the
same destination register, the scoreboard issues the instruction to the functional unit and
updates its internal data structure. This step replaces a portion of the ID step in the MIPS
pipeline. By ensuring that no other active functional unit wants to write its result into the
destination register, we guarantee that WAW hazards cannot be present. If a structural for
WAW hazard exists, then the instruction issue stalls, and no further instructions will issue
until these hazards are cleared. When the issue stage stalls, it causes the buffer between
instruction fetch and issue to fill; if the buffer is a single entry, instruction fetch stalls im-
mediately. If the buffer is a queue with multiple instructions, it stalls when the queue fills.2.
2. Read operands —The scoreboard monitors the availability of the source operands. A source
operand is available if no earlier issued active instruction is going to write it. When the
source operands are available, the scoreboard tells the functional unit to proceed to read
the operands from the registers and begin execution. The scoreboard resolves RAW hazar-
ds dynamically in this step, and instructions may be sent into execution out of order. This
step, together with issue, completes the function of the ID step in the simple MIPS pipeline.
3. Execution —The functional unit begins execution upon receiving operands. When the result
is ready, it notifies the scoreboard that it has completed execution. This step replaces the
EX step in the MIPS pipeline and takes multiple cycles in the MIPS FP pipeline.
4. Write result —Once the scoreboard is aware that the functional unit has completed execu-
tion, the scoreboard checks for WAR hazards and stalls the completing instruction, if ne-
cessary.
A WAR hazard exists if there is a code sequence like our earlier example with ADD.D and
SUB.D that both use F8 . In that example, we had the code
DIV.D F0,F2,F4
ADD.D F10,F0,F8
SUB.D F8,F8,F14
ADD.D has a source operand F8 , which is the same register as the destination of SUB.D . But
ADD.D actually depends on an earlier instruction. The scoreboard will still stall the SUB.D in its
write result stage until ADD.D reads its operands. In general, then, a completing instruction
cannot be allowed to write its results when:
■ There is an instruction that has not read its operands that precedes (i.e., in order of is-
sue) the completing instruction, and
■ One of the operands is the same register as the result of the completing instruction.
If this WAR hazard does not exist, or when it clears, the scoreboard tells the functional unit to
store its result to the destination register. This step replaces the WB step in the simple MIPS
pipeline.
At first glance, it might appear that the scoreboard will have difficulty separating RAW and
WAR hazards.
Because the operands for an instruction are read only when both operands are available in
the register file, this scoreboard does not take advantage of forwarding. Instead, registers are
only read when they are both available. This is not as large a penalty as you might initially
think. Unlike our simple pipeline of earlier, instructions will write their result into the register
file, as soon as they complete execution (assuming no WAR hazards), rather than wait for a
statically assigned write slot that may be several cycles away. The effect is reduced pipeline
latency and benefits of forwarding. There is still one additional cycle of latency that arises
since the write result and read operand stages cannot overlap. We would need additional buf-
fering to eliminate this overhead.
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