Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 688

FIGURE C.54 The basic structure of a MIPS processor with a scoreboard . The score-
board's function is to control instruction execution (vertical control lines). All of the data flow
between the register file and the functional units over the buses (the horizontal lines, called
trunks in the CDC 6600). There are two FP multipliers, an FP divider, an FP adder, and an in-
teger unit. One set of buses (two inputs and one output) serves a group of functional units.
The details of the scoreboard are shown in Figures C.55 to C.58 .
Every instruction goes through the scoreboard, where a record of the data dependences is
constructed; this step corresponds to instruction issue and replaces part of the ID step in the
MIPS pipeline. The scoreboard then determines when the instruction can read its operands
and begin execution. If the scoreboard decides the instruction cannot execute immediately,
it monitors every change in the hardware and decides when the instruction can execute. The
scoreboard also controls when an instruction can write its result into the destination register.
Thus, all hazard detection and resolution are centralized in the scoreboard. We will see a pic-
ture of the scoreboard later ( Figure C.55 on page C-76), but first we need to understand the
steps in the issue and execution segment of the pipeline.