Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 667

1. The main integer unit that handles loads and stores, integer ALU operations, and branches
2. FP and integer multiplier
3. FP adder that handles FP add, subtract, and conversion
4. FP and integer divider
If we also assume that the execution stages of these functional units are not pipelined,
then Figure C.33 shows the resulting pipeline structure. Because EX is not pipelined, no other
instruction using that functional unit may issue until the previous instruction leaves EX.
Moreover, if an instruction cannot proceed to the EX stage, the entire pipeline behind that in-
struction will be stalled.
FIGURE C.33 The MIPS pipeline with three additional unpipelined, floating-point, func-
tional units . Because only one instruction issues on every clock cycle, all instructions go
through the standard pipeline for integer operations. The FP operations simply loop when they
reach the EX stage. After they have finished the EX stage, they proceed to MEM and WB to
complete execution.
In reality, the intermediate results are probably not cycled around the EX unit as Figure C.33
suggests; instead, the EX pipeline stage has some number of clock delays larger than 1. We can
generalize the structure of the FP pipeline shown in Figure C.33 to allow pipelining of some
stages and multiple ongoing operations. To describe such a pipeline, we must define both the
latency of the functional units and also the initiation interval or repeat interval . We define latency
the same way we defined it earlier: the number of intervening cycles between an instruction
that produces a result and an instruction that uses the result. The initiation or repeat interval