Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 659

Dealing With Exceptions
Exceptional situations are harder to handle in a pipelined CPU because the overlapping of in-
structions makes it more difficult to know whether an instruction can safely change the state
of the CPU. In a pipelined CPU, an instruction is executed piece by piece and is not completed
for several clock cycles. Unfortunately, other instructions in the pipeline can raise exceptions
that may force the CPU to abort the instructions in the pipeline before they complete. Before
we discuss these problems and their solutions in detail, we need to understand what types of
situations can arise and what architectural requirements exist for supporting them.
Types of Exceptions and Requirements
The terminology used to describe exceptional situations where the normal execution order of
instruction is changed varies among CPUs. The terms interrupt, fault , and exception are used,
although not in a consistent fashion. We use the term exception to cover all these mechanisms,
including the following:
■ I/O device request
■ Invoking an operating system service from a user program
■ Tracing instruction execution
■ Breakpoint (programmer-requested interrupt)
■ Integer arithmetic overflow
■ FP arithmetic anomaly
■ Page fault (not in main memory)
■ Misaligned memory accesses (if alignment is required)
■ Memory protection violation
■ Using an undefined or unimplemented instruction
■ Hardware malfunctions
■ Power failure
When we wish to refer to some particular class of such exceptions, we will use a longer
name, such as I/O interrupt, floating-point exception, or page fault. Figure C.30 shows the vari-
ety of different names for the common exception events above.