Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 631

or to D ADD , this is not always the case. If an interrupt should occur between the DADD and DSUB
instructions, the WB stage of the DADD will complete, and the value of R1 at that point will be
the result of the DADD . This unpredictable behavior is obviously unacceptable.
FIGURE C.6 The use of the result of the DADD instruction in the next three instructions
causes a hazard, since the register is not written until after those instructions read it .
The AND instruction is also affected by this hazard. As we can see from Figure C.6 , the write
of R1 does not complete until the end of clock cycle 5. Thus, the AND instruction that reads the
registers during clock cycle 4 will receive the wrong results.
The XOR instruction operates properly because its register read occurs in clock cycle 6, after
the register write. The OR instruction also operates without incurring a hazard because we per-
form the register file reads in the second half of the cycle and the writes in the first half.
The next subsection discusses a technique to eliminate the stalls for the hazard involving the
D SUB and AND instructions.
Minimizing Data Hazard Stalls by Forwarding
The problem posed in Figure C.6 can be solved with a simple hardware technique called for-
warding (also called bypassing and sometimes short-circuiting ). The key insight in forwarding is
that the result is not really needed by the DSUB until after the DADD actually produces it. If the res-