Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 630

Clearly, the processor without the structural hazard is faster; we can use the
ratio of the average instruction times to conclude that the processor without the
hazard is 1.3 times faster.
As an alternative to this structural hazard, the designer could provide a sep-
arate memory access for instructions, either by spliting the cache into separate
instruction and data caches or by using a set of buffers, usually called instruc-
tion buffers , to hold instructions. Chapter 5 discusses both the split cache and in-
struction buffer ideas.
If all other factors are equal, a processor without structural hazards will always have a
lower CPI. Why, then, would a designer allow structural hazards? The primary reason is to
reduce cost of the unit, since pipelining all the functional units, or duplicating them, may be
too costly. For example, processors that support both an instruction and a data cache access
every cycle (to prevent the structural hazard of the above example) require twice as much total
memory bandwidth and often have higher bandwidth at the pins. Likewise, fully pipelining
a floating-point (FP) multiplier consumes lots of gates. If the structural hazard is rare, it may
not be worth the cost to avoid it.
Data Hazards
A major effect of pipelining is to change the relative timing of instructions by overlapping
their execution. This overlap introduces data and control hazards. Data hazards occur when
the pipeline changes the order of read/write accesses to operands so that the order differs from
the order seen by sequentially executing instructions on an unpipelined processor. Consider
the pipelined execution of these instructions:
DADD R1,R2,R3
DSUB R4,R1,R5
AND R6,R1,R7
OR R8,R1,R9
XOR R10,R1,R11
All the instructions after the DADD use the result of the DADD instruction. As shown in Figure
C.6 , the D ADD instruction writes the value of R1 in the WB pipe stage, but the DSUB instruction
reads the value during its ID stage. This problem is called a data hazard . Unless precautions are
taken to prevent it, the D SUB instruction will read the wrong value and try to use it. In fact, the
value used by the DSUB instruction is not even deterministic: Though we might think it logical
to assume that D SUB would always use the value of R1 that was assigned by an instruction pri-