Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 629

FIGURE C.5 A pipeline stalled for a structural hazard—a load with one memory port . As
shown here, the load instruction effectively steals an instruction-fetch cycle, causing the
pipeline to stall—no instruction is initiated on clock cycle 4 (which normally would initiate in-
struction i + 3). Because the instruction being fetched is stalled, all other instructions in the
pipeline before the stalled instruction can proceed normally. The stall cycle will continue to
pass through the pipeline, so that no instruction completes on clock cycle 8. Sometimes these
pipeline diagrams are drawn with the stall occupying an entire horizontal row and instruction 3
being moved to the next row; in either case, the effect is the same, since instruction i + 3 does
not begin execution until cycle 5. We use the form above, since it takes less space in the fig-
ure. Note that this figure assumes that instructions i + 1 and i + 2 are not memory references.
Example
Let's see how much the load structural hazard might cost. Suppose that data
references constitute 40% of the mix, and that the ideal CPI of the pipelined pro-
cessor, ignoring the structural hazard, is 1. Assume that the processor with the
structural hazard has a clock rate that is 1.05 times higher than the clock rate of
the processor without the hazard. Disregarding any other performance losses,
is the pipeline with or without the structural hazard faster, and by how much?
Answer
There are several ways we could solve this problem. Perhaps the simplest is to
compute the average instruction time on the two processors:
Since it has no stalls, the average instruction time for the ideal processor is
simply the Clock cycle time ideal . The average instruction time for the processor
with the structural hazard is