Hardware Reference
In-Depth Information
under certain circumstances, the pipeline might want to perform two writes in a clock cycle.
This will generate a structural hazard.
When a sequence of instructions encounters this hazard, the pipeline will stall one of the
instructions until the required unit is available. Such stalls will increase the CPI from its usual
ideal value of 1.
Some pipelined processors have shared a single- memory pipeline for data and instructions.
As a result, when an instruction contains a data memory reference, it will conflict with the in-
struction reference for a later instruction, as shown in Figure C.4 . To resolve this hazard, we
stall the pipeline for 1 clock cycle when the data memory access occurs. A stall is commonly
called a pipeline bubble or just bubble , since it floats through the pipeline taking space but carry-
ing no useful work. We will see another type of stall when we talk about data hazards.
FIGURE C.4 A processor with only one memory port will generate a conflict whenever
a memory reference occurs . In this example the load instruction uses the memory for a data
access at the same time instruction 3 wants to fetch an instruction from memory.
Designers often indicate stall behavior using a simple diagram with only the pipe stage
names, as in Figure C.5 . The form of Figure C.5 shows the stall by indicating the cycle when
no action occurs and simply shifting instruction 3 to the right (which delays its execution start
and finish by 1 cycle). The effect of the pipeline bubble is actually to occupy the resources for
that instruction slot as it travels through the pipeline.
 
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