Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 622

FIGURE C.2 The pipeline can be thought of as a series of data paths shifted in time .
This shows the overlap among the parts of the data path, with clock cycle 5 (CC 5) showing
the steady-state situation. Because the register file is used as a source in the ID stage and as
a destination in the WB stage, it appears twice. We show that it is read in one part of the
stage and written in another by using a solid line, on the right or left, respectively, and a
dashed line on the other side. The abbreviation IM is used for instruction memory, DM for data
memory, and CC for clock cycle.
First, we use separate instruction and data memories, which we would typically implement
with separate instruction and data caches (discussed in Chapter 2 ). The use of separate caches
eliminates a conflict for a single memory that would arise between instruction fetch and data
memory access. Notice that if our pipelined processor has a clock cycle that is equal to that
of the unpipelined version, the memory system must deliver five times the bandwidth. This
increased demand is one cost of higher performance.
Second, the register file is used in the two stages: one for reading in ID and one for writing
in WB. These uses are distinct, so we simply show the register file in two places. Hence, we
need to perform two reads and one write every clock cycle. To handle reads and a write to the
same register (and for another reason, which will become obvious shortly), we perform the re-
gister write in the first half of the clock cycle and the read in the second half.
Third, Figure C.2 does not deal with the PC. To start a new instruction every clock, we must
increment and store the PC every clock, and this must be done during the IF stage in prepar-
ation for the next instruction. Furthermore, we must also have an adder to compute the po-
tential branch target during ID. One further problem is that a branch does not change the PC
until the ID stage. This causes a problem, which we ignore for now, but will handle shortly.