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c. [15] <B.4> Are there page table structures that would be difficult to handle in hardware
but possible in software? Are there any such structures that would be difficult for soft-
ware to handle but easy for hardware to manage?
d. [15] <B.4> Why are TLB miss rates for floating-point programs generally higher than
those for integer programs?
B.14 [25/25/25/25/20] <B.4> How big should a TLB be? TLB misses are usually very fast
(fewer than 10 instructions plus the cost of an exception), so it may not be worth having
a huge TLB just to lower the TLB miss rate a bit. Using the SimpleScalar simulator
( www.cs.wisc.edu/~mscalar/simplescalar.html ) and one or more SPEC95 benchmarks, calcu-
late the TLB miss rate and the TLB overhead (in percentage of time wasted handling TLB
misses) for the following TLB configurations. Assume that each TLB miss requires 20 in-
structions.
a. [25] <B.4> 128 entries, two-way set associative, 4 KB to 64 KB pages (going by powers
of 2).
b. [25] <B.4> 256 entries, two-way set associative, 4 KB to 64 KB pages (going by powers
of 2).
c. [25] <B.4> 512 entries, two-way set associative, 4 KB to 64 KB pages (going by powers
of 2).
d. [25] <B.4> 1024 entries, two-way set associative, 4 KB to 64 KB pages (going by powers
of 2).
e. [20] <B.4> What would be the effect on TLB miss rate and overhead for a multitasking
environment? How would the context switch frequency affect the overhead?
B.15 [15/20/20] <B.5> It is possible to provide more flexible protection than that in the Intel
Pentium architecture by using a protection scheme similar to that used in the Hewlet-
Packard Precision Architecture (HP/PA). In such a scheme, each page table entry contains
a “protection ID” (key) along with access rights for the page. On each reference, the CPU
compares the protection ID in the page table entry with those stored in each of four pro-
tection ID registers (access to these registers requires that the CPU be in supervisor model
If there is no match for the protection ID in the page table entry or if the access is not a
permitted access (writing to a read-only page, for example), an exception is generated.
a. [15] <B.5> How could a process have more than four valid protection IDs at any given
time? In other words, suppose a process wished to have 10 protection IDs simultan-
eously. Propose a mechanism by which this could be done (perhaps with help from
software).
b. [20] <B.5> Explain how this model could be used to facilitate the construction of oper-
ating systems from relatively small pieces of code that can't overwrite each other (mi-
crokernels). What advantages might such an operating system have over a monolithic
operating system in which any code in the OS can write to any memory location?
c. [20] <B.5> A simple design change to this system would allow two protection IDs for
each page table entry, one for read access and the other for either write or execute ac-
cess (the field is unused if neither the writable nor executable bit is set). What advant-
ages might there be from having different protection IDs for read and write capabilit-
ies? ( Hint : Could this make it easier to share data and code between processes?)
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