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e. [15] <B.1> Repeat part (c) assuming that logic is added to predict the cache way to be
accessed. Only the tag sub-array for the predicted way is accessed in cycle one. A way
hit (address match in predicted way) implies a cache hit. A way miss dictates examin-
ing all the tag sub-arrays in the second cycle. In case of a way hit, only one data sub-
array (the one whose tag matched) is accessed in cycle two. Assume there is way hit.
f. [10] <B.1> Repeat part (e) assuming that the way predictor missed (the way it chose is
wrong). When it fails, the way predictor adds an extra cycle in which it accesses all the
tag sub-arrays. Assume a cache read hit.
g. [15] <B.1> Repeat part (f) assuming a cache read miss.
h. [20] <B.1> Use parts (e), (f), and (g) for the general case where the workload has the
following statistics: way-predictor miss rate = 5% and cache miss rate = 3%. (Consider
diferent replacement policies.)
B.4 [10/10/15/15/15/20] <B.1> We compare the write bandwidth requirements of write-
through versus write-back caches using a concrete example. Let us assume that we have a
64 KB cache with a line size of 32 bytes. The cache will allocate a line on a write miss. If
conigured as a write-back cache, it will write back the whole dirty line if it needs to be re-
placed. We will also assume that the cache is connected to the lower level in the hierarchy
through a 64-bit-wide (8-byte-wide) bus. The number of CPU cycles for a B-bytes write ac-
cess on this bus is
For example, an 8-byte write would take cycles, whereas using the
same formula a 12-byte write would take 15 cycles. Answer the following questions while
referring to the C code snippet below:
#define PORTION 1 … Base = 8*i; for (unsigned int j=base;
j < base+PORTION; j++) //assume j is stored in a register
data[j] = j;
a. [10] <B.1> For a write-through cache, how many CPU cycles are spent on write trans-
fers to the memory for the all the combined iterations of the j loop?
b. [10] <B.1> If the cache is configured as a write-back cache, how many CPU cycles are
spent on writing back a cache line?
c. [15] <B.1> Change PORTION to 8 and repeat part (a).
d. [15] <B.1> What is the minimum number of array updates to the same cache line (be-
fore replacing it) that would render the write-back cache superior?
e. [15] <B.1> Think of a scenario where all the words of the cache line will be writen (not
necessarily using the above code) and a write-through cache will require fewer total
CPU cycles than the write-back cache.
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