Hardware Reference
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FIGURE B.30 Memory blocks that can reside in cache block .
B.3 [10/10/10/10/15/10/15/20] <B.1> Cache organization is often influenced by the desire to re-
duce the cache's power consumption. For that purpose we assume that the cache is phys-
ically distributed into a data array (holding the data), tag array (holding the tags), and re-
placement array (holding information needed by replacement policy). Furthermore, every
one of these arrays is physically distributed into multiple sub-arrays (one per way) that
can be individually accessed; for example, a four-way set associative least recently used
(LRU) cache would have four data sub-arrays, four tag sub-arrays, and four replacement
sub-arrays. We assume that the replacement sub-arrays are accessed once per access when
the LRU replacement policy is used, and once per miss if the first-in, first-out (FIFO) re-
placement policy is used. It is not needed when a random replacement policy is used. For
a specific cache, it was determined that the accesses to the different arrays have the follow-
ing power consumption weights:
Array
Power consumption weight (per way accessed)
Data array
20 units
Tag
Array 5 units
Miscellaneous array
1 unit
Estimate the cache power usage (in power units) for the following configurations. We assume
the cache is four-way set associative. Main memory access power—albeit important—is not
considered here. Provide answers for the LRU, FIFO, and random replacement policies.
a. [10]<B.1> A cache read hit. All arrays are read simultaneously.
b. [10] <B.1> Repeat part (a) for a cache read miss.
c. [10] <B.1> Repeat part (a) assuming that the cache access is split across two cycles. In
the first cycle, all the tag sub-arrays are accessed. In the second cycle, only the sub-ar-
ray whose tag matched will be accessed.
d. [10] <B.1> Repeat part (c) for a cache read miss (no data array accesses in the second
cycle).
 
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