Hardware Reference
In-Depth Information
Page size —Says whether the last level is for 4 KB pages or 4 MB pages; if it's the later, then
the Opteron only uses three instead of four levels of pages.
No execute —Not found in the 80386 protection scheme, this bit was added to prevent code
from executing in some pages.
Page level cache disable —Says whether the page can be cached or not.
Page level write-through —Says whether the page allows write-back or write-through for data
caches.
Since the Opteron normally goes through four levels of tables on a TLB miss, there are three
potential places to check protection restrictions. The Opteron obeys only the botom-level PTE,
checking the others only to be sure the valid bit is set.
As the entry is 8 bytes long, each page table has 512 entries, and the Opteron has 4 KB pages,
the page tables are exactly one page long. Each of the four level fields are 9 bits long, and the
page offset is 12 bits. This derivation leaves 64 − (4 × 9 + 12) or 16 bits to be sign extended to
ensure canonical addresses.
Although we have explained translation of legal addresses, what prevents the user from
creating illegal address translations and geting into mischief? The page tables themselves are
protected from being writen by user programs. Thus, the user can try any virtual address, but
by controlling the page table entries the operating system controls what physical memory is
accessed. Sharing of memory between processes is accomplished by having a page table entry
in each address space point to the same physical memory page.
The Opteron employs four TLBs to reduce address translation time, two for instruction ac-
cesses and two for data accesses. Like multilevel caches, the Opteron reduces TLB misses by
having two larger L2 TLBs: one for instructions and one for data. Figure B.28 describes the
data TLB.
FIGURE B.28 Memory hierarchy parameters of the Opteron L1 and L2 instruction and
data TLBs .
 
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