Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 604

IA-32 hardware then uses the requested protection level to prevent any foolishness: No seg-
ment can be accessed from the system routine using those parameters if it has a more priv-
ileged protection level than requested.
A Paged Virtual Memory Example: The 64-Bit Opteron Memory
Management
AMD engineers found few uses of the elaborate protection model described above. The pop-
ular model is a flat, 32-bit address space, introduced by the 80386, which sets all the base val-
ues of the segment registers to zero. Hence, AMD dispensed with the multiple segments in
the 64-bit mode. It assumes that the segment base is zero and ignores the limit field. The page
sizes are 4 KB, 2 MB, and 4 MB.
The 64-bit virtual address of the AMD64 architecture is mapped onto 52-bit physical ad-
dresses, although implementations can implement fewer bits to simplify hardware. The Opter-
on, for example, uses 48-bit virtual addresses and 40-bit physical addresses. AMD64 requires
that the upper 16 bits of the virtual address be just the sign extension of the lower 48 bits,
which it calls canonical form .
The size of page tables for the 64-bit address space is alarming. Hence, AMD64 uses a mul-
tilevel hierarchical page table to map the address space to keep the size reasonable. The num-
ber of levels depends on the size of the virtual address space. Figure B.27 shows the four-level
translation of the 48-bit virtual addresses of the Opteron.