Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 598

FIGURE B.25 The overall picture of a hypothetical memory hierarchy going from virtual
address to L2 cache access . The page size is 8 KB. The TLB is direct mapped with 256
entries. The L1 cache is a direct-mapped 8 KB, and the L2 cache is a direct-mapped 4 MB.
Both use 64-byte blocks. The virtual address is 64 bits and the physical address is 41 bits.
The primary difference between this simple figure and a real cache is replication of pieces of
this figure.
First, the 64-bit virtual address is logically divided into a virtual page number and page of-
set. The former is sent to the TLB to be translated into a physical address, and the high bit of
the later is sent to the L1 cache to act as an index. If the TLB match is a hit, then the physical
page number is sent to the L1 cache tag to check for a match. If it matches, it's an L1 cache hit.
The block offset then selects the word for the processor.
If the L1 cache check results in a miss, the physical address is then used to try the L2 cache.
The middle portion of the physical address is used as an index to the 4 MB L2 cache. The res-
ulting L2 cache tag is compared to the upper part of the physical address to check for a match.
If it matches, we have an L2 cache hit, and the data are sent to the processor, which uses the
block offset to select the desired word. On an L2 miss, the physical address is then used to get
the block from memory.