Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 596

match. At the same time, the type of memory access is checked for a violation (also in step 2)
against protection information in the TLB.
FIGURE B.24 Operation of the Opteron data TLB during address translation . The four
steps of a TLB hit are shown as circled numbers. This TLB has 40 entries. Section B.5 de-
scribes the various protection and access fields of an Opteron page table entry.
For reasons similar to those in the cache case, there is no need to include the 12 bits of the
page offset in the TLB. The matching tag sends the corresponding physical address through
efectively a 40:1 multiplexor (step 3). The page offset is then combined with the physical page
frame to form a full physical address (step 4). The address size is 40 bits.
Address translation can easily be on the critical path determining the clock cycle of the pro-
cessor, so the Opteron uses virtually addressed, physically tagged L1 caches.
Selecting A Page Size
The most obvious architectural parameter is the page size. Choosing the page is a question of
balancing forces that favor a larger page size versus those favoring a smaller size. The follow-
ing favor a larger size:
■ The size of the page table is inversely proportional to the page size; memory (or other re-
sources used for the memory map) can therefore be saved by making the pages bigger.
■ As mentioned in Section B.3 , a larger page size can allow larger caches with fast cache hit
times.
■ Transferring larger pages to or from secondary storage, possibly over a network, is more
eicient than transferring smaller pages.
■ The number of TLB entries is restricted, so a larger page size means that more memory can
be mapped efficiently, thereby reducing the number of TLB misses.
It is for this final reason that recent microprocessors have decided to support multiple page
sizes; for some programs, TLB misses can be as significant on CPI as the cache misses.
The main motivation for a smaller page size is conserving storage. A small page size will
result in less wasted storage when a contiguous region of virtual memory is not equal in size
to a multiple of the page size. The term for this unused memory in a page is internal fragment-