Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 589

FIGURE B.17 The overall picture of a hypothetical memory hierarchy going from virtual
address to L2 cache access . The page size is 16 KB. The TLB is two-way set associative
with 256 entries. The L1 cache is a direct-mapped 16 KB, and the L2 cache is a four-way set
associative with a total of 4 MB. Both use 64-byte blocks. The virtual address is 64 bits and
the physical address is 40 bits.
Associativity can keep the index in the physical part of the address and yet still support a
large cache. Recall that the size of the index is controlled by this formula:
For example, doubling associativity and doubling the cache size does not change the size of
the index. The IBM 3033 cache, as an extreme example, is 16-way set associative, even though
studies show there is litle beneit to miss rates above 8-way set associativity. This high associ-