Hardware Reference
In-Depth Information
Software can make this problem much easier by forcing aliases to share some address bits.
An older version of UNIX from Sun Microsystems, for example, required all aliases to be
identical in the last 18 bits of their addresses; this restriction is called page coloring . Note that
page coloring is simply set associative mapping applied to virtual memory: The 4 KB (2 12 )
pages are mapped using 64 (2 6 ) sets to ensure that the physical and virtual addresses match in
the last 18 bits. This restriction means a direct-mapped cache that is 2 18 (256K) bytes or smal-
ler can never have duplicate physical addresses for blocks. From the perspective of the cache,
page coloring effectively increases the page offset, as software guarantees that the last few bits
of the virtual and physical page address are identical.
The final area of concern with virtual addresses is I/O. I/O typically uses physical addresses
and thus would require mapping to virtual addresses to interact with a virtual cache. (The im-
pact of I/O on caches is further discussed in Appendix D.)
One alternative to get the best of both virtual and physical caches is to use part of the page
ofset—the part that is identical in both virtual and physical addresses—to index the cache.
At the same time as the cache is being read using that index, the virtual part of the address is
translated, and the tag match uses physical addresses.
This alternative allows the cache read to begin immediately, and yet the tag comparison is
still with physical addresses. The limitation of this virtually indexed, physically tagged alternat-
ive is that a direct-mapped cache can be no bigger than the page size. For example, in the data
cache in Figure B.5 on page B-13, the index is 9 bits and the cache block offset is 6 bits. To use
this trick, the virtual page size would have to be at least 2 (9+6) bytes or 32 KB. If not, a portion
of the index must be translated from virtual to physical address. Figure B.17 shows the or-
ganization of the caches, translation lookaside buffers (TLBs), and virtual memory when this
technique is used.
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