Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 585

However, what if the designer can only afford an L2 cache that is slightly bigger than the L1
cache? Should a significant portion of its space be used as a redundant copy of the L1 cache?
In such cases a sensible opposite policy is multilevel exclusion: L1 data are never found in an
L2 cache. Typically, with exclusion a cache miss in L1 results in a swap of blocks between L1
and L2 instead of a replacement of an L1 block with an L2 block. This policy prevents wasting
space in the L2 cache. For example, the AMD Opteron chip obeys the exclusion property using
two 64 KB L1 caches and 1 MB L2 cache.
As these issues illustrate, although a novice might design the first- and second-level caches
independently, the designer of the first-level cache has a simpler job given a compatible
second-level cache. It is less of a gamble to use a write-through, for example, if there is a write-
back cache at the next level to act as a backstop for repeated writes and it uses multilevel in-
clusion.
The essence of all cache designs is balancing fast hits and few misses. For second-level
caches, there are many fewer hits than in the first-level cache, so the emphasis shifts to fewer
misses. This insight leads to much larger caches and techniques to lower the miss rate, such as
higher associativity and larger blocks.
Fifth Optimization: Giving Priority To Read Misses Over Writes
To Reduce Miss Penalty
This optimization serves reads before writes have been completed. We start with looking at
the complexities of a write buffer
With a write-through cache the most important improvement is a write buffer of the proper
size. Write buffers, however, do complicate memory accesses because they might hold the up-
dated value of a location needed on a read miss.
Example
Look at this code sequence:
SW R3, 512(R0) ;M[512] ← R3 (cache index 0)
LW R1, 1024(R0) ;R1 ← M[1024] (cache index 0)
LW R2, 512(R0) ;R2 ← M[512] (cache index 0)
Assume a direct-mapped, write-through cache that maps 512 and 1024 to the
same block, and a four-word write buffer that is not checked on a read miss.
Will the value in R2 always be equal to the value in R3?
Answer
Using the terminology from Chapter 2 , this is a read-after-write data hazard in
memory. Let's follow a cache access to see the danger. The data in R3 are placed
into the write buffer after the store. The following load uses the same cache in-
dex and is therefore a miss. The second load instruction tries to put the value in
location 512 into register R2; this also results in a miss. If the write buffer hasn't
completed writing to location 512 in memory, the read of location 512 will put
the old, wrong value into the cache block, and then into R2. Without proper pre-
cautions, R3 would not be equal to R2!