Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 577

The second observation, called the 2:1 cache rule of thumb , is that a direct-mapped cache of
size N has about the same miss rate as a two-way set associative cache of size N/2 . This held in
three C's figures for cache sizes less than 128 KB.
Like many of these examples, improving one aspect of the average memory access time
comes at the expense of another. Increasing block size reduces miss rate while increasing miss
penalty, and greater associativity can come at the cost of increased hit time. Hence, the pres-
sure of a fast processor clock cycle encourages simple cache designs, but the increasing miss
penalty rewards associativity, as the following example suggests.
Example
Assume that higher associativity would increase the clock cycle time as listed
below:
Assume that the hit time is 1 clock cycle, that the miss penalty for the direct-
mapped case is 25 clock cycles to a level 2 cache (see next subsection) that never
misses, and that the miss penalty need not be rounded to an integral number of
clock cycles. Using Figure B.8 for miss rates, for which cache sizes are each of
these three statements true?
Answer
Average memory access time for each associativity is