Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 574

FIGURE B.10 Miss rate versus block size for five different-sized caches . Note that miss
rate actually goes up if the block size is too large relative to the cache size. Each line repres-
ents a cache of different size. Figure B.11 shows the data used to plot these lines. Unfortu-
nately, SPEC2000 traces would take too long if block size were included, so these data are
based on SPEC92 on a DECstation 5000 [Gee et al. 1993].
At the same time, larger blocks increase the miss penalty. Since they reduce the number of
blocks in the cache, larger blocks may increase conflict misses and even capacity misses if the
cache is small. Clearly, there is litle reason to increase the block size to such a size that it in-
creases the miss rate. There is also no benefit to reducing miss rate if it increases the average
memory access time. The increase in miss penalty may outweigh the decrease in miss rate.
Example
Figure B.11 shows the actual miss rates ploted in Figure B.10 . Assume the
memory system takes 80 clock cycles of overhead and then delivers 16 bytes
every 2 clock cycles. Thus, it can supply 16 bytes in 82 clock cycles, 32 bytes in
84 clock cycles, and so on. Which block size has the smallest average memory
access time for each cache size in Figure B.11 ?