Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 566

Although minimizing average memory access time is a reasonable goal—and we will use it
in much of this appendix—keep in mind that the final goal is to reduce processor execution
time. The next example shows how these two can differ.
Example
What is the impact of two different cache organizations on the performance of
a processor? Assume that the CPI with a perfect cache is 1.6, the clock cycle
time is 0.35 ns, there are 1.4 memory references per instruction, the size of both
caches is 128 KB, and both have a block size of 64 bytes. One cache is direct
mapped and the other is two-way set associative. Figure B.5 shows that for set
associative caches we must add a multiplexor to select between the blocks in
the set depending on the tag match. Since the speed of the processor can be tied
directly to the speed of a cache hit, assume the processor clock cycle time must
be stretched 1.35 times to accommodate the selection multiplexor of the set as-
sociative cache. To the first approximation, the cache miss penalty is 65 ns for
either cache organization. (In practice, it is normally rounded up or down to an
integer number of clock cycles.) First, calculate the average memory access time
and then processor performance. Assume the hit time is 1 clock cycle, the miss
rate of a direct-mapped 128 KB cache is 2.1%, and the miss rate for a two-way
set associative cache of the same size is 1.9%.
Answer
Average memory access time is
Thus, the time for each organization is
The average memory access time is beter for the two-way set-associative
cache.
The processor performance is