Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 565

The performance, including cache misses, is
Now calculating performance using miss rate:
The clock cycle time and instruction count are the same, with or without a
cache. Thus, CPU time increases sevenfold, with CPI from 1.00 for a “perfect
cache” to 7.00 with a cache that can miss. Without any memory hierarchy at all
the CPI would increase again to 1.0 + 200 × 1.5 or 301—a factor of more than 40
times longer than a system with a cache!
As this example illustrates, cache behavior can have enormous impact on performance. Fur-
thermore, cache misses have a double-barreled impact on a processor with a low CPI and a
fast clock:
1. The lower the CPI execution , the higher the relative impact of a fixed number of cache miss clock
cycles.
2. When calculating CPI, the cache miss penalty is measured in processor clock cycles for a
miss. Therefore, even if memory hierarchies for two computers are identical, the processor
with the higher clock rate has a larger number of clock cycles per miss and hence a higher
memory portion of CPI.
The importance of the cache for processors with low CPI and high clock rates is thus greater,
and, consequently, greater is the danger of neglecting cache behavior in assessing perform-
ance of such computers. Amdahl's law strikes again!