Hardware Reference
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The advantage of the last form is that the components can be easily measured. We already
know how to measure instruction count (IC). (For speculative processors, we only count in-
structions that commit.) Measuring the number of memory references per instruction can be
done in the same fashion; every instruction requires an instruction access, and it is easy to de-
cide if it also requires a data access.
Note that we calculated miss penalty as an average, but we will use it below as if it were a
constant. The memory behind the cache may be busy at the time of the miss because of pri-
or memory requests or memory refresh. The number of clock cycles also varies at interfaces
between different clocks of the processor, bus, and memory. Thus, please remember that using
a single number for miss penalty is a simpliication.
The component
miss rate
is simply the fraction of cache accesses that result in a miss (i.e.,
number of accesses that miss divided by number of accesses). Miss rates can be measured with
cache simulators that take an
address trace
of the instruction and data references, simulate the
cache behavior to determine which references hit and which miss, and then report the hit and
miss totals. Many microprocessors today provide hardware to count the number of misses and
memory references, which is a much easier and faster way to measure miss rate.
The formula above is an approximation since the miss rates and miss penalties are often
different for reads and writes. Memory stall clock cycles could then be defined in terms of
the number of memory accesses per instruction, miss penalty (in clock cycles) for reads and
writes, and miss rate for reads and writes:
We normally simplify the complete formula by combining the reads and writes and inding
the average miss rates and miss penalty for reads
and
writes:
The miss rate is one of the most important measures of cache design, but, as we will see in
later sections, not the only measure.
Example
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