Review of Memory Hierarchy - Computer Architecture: A Quantitative Approach - page 549

Figure B.1 shows the range of sizes and access times of each level in the memory hierarchy
for computers ranging from high-end desktops to low-end servers.
FIGURE B.1 The typical levels in the hierarchy slow down and get larger as we move
away from the processor for a large workstation or small server . Embedded computers
might have no disk storage and much smaller memories and caches. The access times in-
crease as we move to lower levels of the hierarchy, which makes it feasible to manage the
transfer less responsively. The implementation technology shows the typical technology used
for these functions. The access time is given in nanoseconds for typical values in 2006; these
times will decrease over time. Bandwidth is given in megabytes per second between levels in
the memory hierarchy. Bandwidth for disk storage includes both the media and the buffered
interfaces.
Cache Performance Review
Because of locality and the higher speed of smaller memories, a memory hierarchy can sub-
stantially improve performance. One method to evaluate cache performance is to expand our
processor execution time equation from Chapter 1 . We now account for the number of cycles
during which the processor is stalled waiting for a memory access, which we call the memory
stall cycles . The performance is then the product of the clock cycle time and the sum of the pro-
cessor cycles and the memory stall cycles:
This equation assumes that the CPU clock cycles include the time to handle a cache hit and
that the processor is stalled during a cache miss. Section B.2 reexamines this simplifying as-
sumption.
The number of memory stall cycles depends on both the number of misses and the cost per
miss, which is called the miss penalty: