Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 541

a. [20] <A.2, A.9> Write the code for MIPS. How many instructions are required dynam-
ically? How many memory-data references will be executed? What is the code size in
bytes?
b. [20] <A.2> Write the code for ×86. How many instructions are required dynamically?
How many memory-data references will be executed? What is the code size in bytes?
A.8 [10/10/10] <A.2, A.7> For the following we consider instruction encoding for instruction
set architectures.
a. [10] <A.2, A.7> Consider the case of a processor with an instruction length of 12 bits
and with 32 general-purpose registers so the size of the address fields is 5 bits. Is it
possible to have instruction encodings for the following?
■ 3 two-address instructions
■ 30 one-address instructions
■ 45 zero-address instructions
b. [10] <A.2, A.7> Assuming the same instruction length and address field sizes as above,
determine if it is possible to have
■ 3 two-address instructions
■ 31 one-address instructions
■ 35 zero-address instructions
Explain your answer.
c. [10] <A.2, A.7> Assume the same instruction length and address field sizes as above.
Further assume there are already 3 two-address and 24 zero-address instructions.
What is the maximum number of one-address instructions that can be encoded for this
processor?
A.9 [10/15] <A.2> For the following assume that values A , B , C , D , E , and F reside in memory.
Also assume that instruction operation codes are represented in 8 bits, memory addresses
are 64 bits, and register addresses are 6 bits.
a. [10] <A.2> For each instruction set architecture shown in Figure A.2 , how many ad-
dresses, or names, appear in each instruction for the code to compute C = A + B , and
what is the total code size?
b. [15] <A.2> Some of the instruction set architectures in Figure A.2 destroy operands
in the course of computation. This loss of data values from processor internal storage
has performance consequences. For each architecture in Figure A.2 , write the code se-
quence to compute:
C = A + B
D = A - E
F = C + D
In your code, mark each operand that is destroyed during execution and mark each
“overhead” instruction that is included just to overcome this loss of data from pro-
cessor internal storage. What is the total code size, the number of bytes of instructions
and data moved to or from memory, the number of overhead instructions, and the
number of overhead data bytes for each of your code sequences?
A.10 [20] <A.2, A.7, A.9> The design of MIPS provides for 32 general-purpose registers and
32 loating-point registers. If registers are good, are more registers beter? List and discuss
as many trade-offs as you can that should be considered by instruction set architecture de-
signers examining whether to, and how much to, increase the number of MIPS registers.