Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 538

VAX designers overemphasized the importance of code size efficiency, underestimating how
important ease of decoding and pipelining would be five years later. An example in the RISC
camp is delayed branch (see Appendix K). It was a simple mater to control pipeline hazards
with five-stage pipelines, but a challenge for processors with longer pipelines that issue mul-
tiple instructions per clock cycle. In addition, almost all architectures eventually succumb to
the lack of sufficient address space.
In general, avoiding such flaws in the long run would probably mean compromising the ef-
iciency of the architecture in the short run, which is dangerous, since a new instruction set
architecture must struggle to survive its first few years.
A.11 Concluding Remarks
The earliest architectures were limited in their instruction sets by the hardware technology of
that time. As soon as the hardware technology permited, computer architects began looking
for ways to support high-level languages. This search led to three distinct periods of thought
about how to support programs efficiently. In the 1960s, stack architectures became popular.
They were viewed as being a good match for high-level languages—and they probably were,
given the compiler technology of the day. In the 1970s, the main concern of architects was how
to reduce software costs. This concern was met primarily by replacing software with hard-
ware, or by providing high-level architectures that could simplify the task of software design-
ers. The result was both the high-level language computer architecture movement and power-
ful architectures like the VAX, which has a large number of addressing modes, multiple data
types, and a highly orthogonal architecture. In the 1980s, more sophisticated compiler techno-
logy and a renewed emphasis on processor performance saw a return to simpler architectures,
based mainly on the load-store style of computer.
The following instruction set architecture changes occurred in the 1990s:
■ Address size doubles —The 32-bit address instruction sets for most desktop and server pro-
cessors were extended to 64-bit addresses, expanding the width of the registers (among
other things) to 64 bits. Appendix K gives three examples of architectures that have gone
from 32 bits to 64 bits.
■ Optimization of conditional branches via conditional execution —In Chapter 3 , we see that con-
ditional branches can limit the performance of aggressive computer designs. Hence, there
was interest in replacing conditional branches with conditional completion of operations,
such as conditional move (see Appendix H), which was added to most instruction sets.
■ Optimization of cache performance via prefetch — Chapter 2 explains the increasing role of
memory hierarchy in the performance of computers, with a cache miss on some computers
taking as many instruction times as page faults took on earlier computers. Hence, prefetch
instructions were added to try to hide the cost of cache misses by prefetching (see Chapter
2 ) .
■ Support for multimedia —Most desktop and embedded instruction sets were extended with
support for multimedia applications.
■ Faster floating-point operations — Appendix J describes operations added to enhance
floating-point performance, such as operations that perform a multiply and an add and
paired single execution. (We include them in MIPS.)
Between 1970 and 1985 many thought the primary job of the computer architect was the
design of instruction sets. As a result, textbooks of that era emphasize instruction set design,
much as computer architecture textbooks of the 1950s and 1960s emphasized computer arith-