Hardware Reference
In-Depth Information
represent true); otherwise, they place the value 0. Because these operations “set” a register,
they are called set-equal, set-not-equal, set-less-than, and so on. There are also immediate
forms of these compares.
Control is handled through a set of jumps and a set of branches. Figure A.25 gives some
typical branch and jump instructions. The four jump instructions are differentiated by the two
ways to specify the destination address and by whether or not a link is made. Two jumps use
a 26-bit offset shifted 2 bits and then replace the lower 28 bits of the program counter (of the
instruction sequentially following the jump) to determine the destination address. The other
two jump instructions specify a register that contains the destination address. There are two
lavors of jumps: plain jump and jump and link (used for procedure calls). The latter places
the return address—the address of the next sequential instruction—in R31.
FIGURE A.25 Typical control flow instructions in MIPS . All control instructions, except
jumps to an address in a register, are PC-relative. Note that the branch distances are longer
than the address field would suggest; since MIPS instructions are all 32 bits long, the byte
branch address is multiplied by 4 to get a longer distance.
All branches are conditional. The branch condition is specified by the instruction, which
may test the register source for zero or nonzero; the register may contain a data value or the
result of a compare. There are also conditional branch instructions to test for whether a re-
gister is negative and for equality between two registers. The branch-target address is speci-
ied with a 16-bit signed offset that is shifted left two places and then added to the program
counter, which is pointing to the next sequential instruction. There is also a branch to test the
floating-point status register for floating-point conditional branches, described later.
Appendix C and Chapter 3 show that conditional branches are a major challenge to
pipelined execution; hence, many architectures have added instructions to convert a simple
branch into a conditional arithmetic instruction. MIPS included conditional move on zero or
not zero. The value of the destination register either is left unchanged or is replaced by a copy
of one of the source registers depending on whether or not the value of the other source re-
gister is zero.
 
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