Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 516

add EAX,1000(EBX)
The name add means a 32-bit integer add instruction with two operands, and this opcode
takes 1 byte. An 80×86 address specifier is 1 or 2 bytes, specifying the source/destination re-
gister ( EAX ) and the addressing mode (displacement in this case) and base register ( EBX ) for the
second operand. This combination takes 1 byte to specify the operands. When in 32-bit mode
(see Appendix K), the size of the address field is either 1 byte or 4 bytes. Since 1000 is bigger
than 2 8 , the total length of the instruction is
The length of 80×86 instructions varies between 1 and 17 bytes. 80×86 programs are gener-
ally smaller than the RISC architectures, which use fixed formats (see Appendix K).
Given these two poles of instruction set design of variable and fixed, the third alternative
immediately springs to mind: Reduce the variability in size and work of the variable architec-
ture but provide multiple instruction lengths to reduce code size. This hybrid approach is the
third encoding alternative, and we'll see examples shortly.
Reduced Code Size In RISCs
As RISC computers started being used in embedded applications, the 32-bit fixed format be-
came a liability since cost and hence smaller code are important. In response, several main
ufacturers offered a new hybrid version of their RISC instruction sets, with both 16-bit and
32-bit instructions. The narrow instructions support fewer operations, smaller address and im-
mediate fields, fewer registers, and the two-address format rather than the classic three-ad-
dress format of RISC computers. Appendix K gives two examples, the ARM Thumb and MIPS
MIPS16, which both claim a code size reduction of up to 40%.
In contrast to these instruction set extensions, IBM simply compresses its standard instruc-
tion set and then adds hardware to decompress instructions as they are fetched from memory
on an instruction cache miss. Thus, the instruction cache contains full 32-bit instructions, but
compressed code is kept in main memory, ROMs, and the disk. The advantage of MIPS16 and
Thumb is that instruction caches act as if they are about 25% larger, while IBM's CodePack
means that compilers need not be changed to handle different instruction sets and instruction
decoding can remain simple.
CodePack starts with run-length encoding compression on any PowerPC program and then
loads the resulting compression tables in a 2 KB table on chip. Hence, every program has its
own unique encoding. To handle branches, which are no longer to an aligned word bound-
ary, the PowerPC creates a hash table in memory that maps between compressed and uncom-
pressed addresses. Like a TLB (see Chapter 2 ) , it caches the most recently used address maps
to reduce the number of memory accesses. IBM claims an overall performance cost of 10%,
resulting in a code size reduction of 35% to 40%.
Hitachi simply invented a RISC instruction set with a fixed 16-bit format, called SuperH, for
embedded applications (see Appendix K). It has 16 rather than 32 registers to make it it the
narrower format and fewer instructions but otherwise looks like a classic RISC architecture.