Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 514

today use a combination of the two mechanisms. This convention is specified in an applica-
tion binary interface (ABI) that sets down the basic rules as to which registers should be caller
saved and which should be callee saved. Later in this appendix we will examine the mis-
match between sophisticated instructions for automatically saving registers and the needs of
the compiler.
Summary: Instructions For Control Flow
Control flow instructions are some of the most frequently executed instructions. Although
there are many options for conditional branches, we would expect branch addressing in a new
architecture to be able to jump to hundreds of instructions either above or below the branch.
This requirement suggests a PC-relative branch displacement of at least 8 bits. We would also
expect to see register indirect and PC-relative addressing for jump instructions to support re-
turns as well as many other features of current systems.
We have now completed our instruction architecture tour at the level seen by an assembly
language programmer or compiler writer. We are leaning toward a load-store architecture
with displacement, immediate, and register indirect addressing modes. These data are 8-, 16-,
32-, and 64-bit integers and 32- and 64-bit floating-point data. The instructions include simple
operations, PC-relative conditional branches, jump and link instructions for procedure call,
and register indirect jumps for procedure return (plus a few other uses).
Now we need to select how to represent this architecture in a form that makes it easy for the
hardware to execute.
A.7 Encoding an Instruction Set
Clearly, the choices mentioned above will affect how the instructions are encoded into a binary
representation for execution by the processor. This representation affects not only the size of
the compiled program but also the implementation of the processor, which must decode this
representation to quickly find the operation and its operands. The operation is typically speci-
field in one field, called the opcode . As we shall see, the important decision is how to encode the
addressing modes with the operations.
This decision depends on the range of addressing modes and the degree of independence
between opcodes and modes. Some older computers have one to five operands with 10 ad-
dressing modes for each operand (see Figure A.6 ). For such a large number of combinations,
typically a separate address specifier is needed for each operand: The address specifier tells what
addressing mode is used to access the operand. At the other extreme are load-store computers
with only one memory operand and only one or two addressing modes; obviously, in this
case, the addressing mode can be encoded as part of the opcode.
When encoding the instructions, the number of registers and the number of addressing
modes both have a significant impact on the size of instructions, as the register field and ad-
dressing mode field may appear many times in a single instruction. In fact, for most instruc-
tions many more bits are consumed in encoding addressing modes and register fields than in
specifying the opcode. The architect must balance several competing forces when encoding
the instruction set:
1. The desire to have as many registers and addressing modes as possible.
2. The impact of the size of the register and addressing mode fields on the average instruction
size and hence on the average program size.