Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 502

Figure A.7 shows the results of measuring addressing mode usage paterns in three pro-
grams on the VAX architecture. We use the old VAX architecture for a few measurements in
this appendix because it has the richest set of addressing modes and the fewest restrictions
on memory addressing. For example, Figure A.6 on page A-9 shows all the modes the VAX
supports. Most measurements in this appendix, however, will use the more recent register-re-
gister architectures to show how programs use instruction sets of current computers.
FIGURE A.7 Summary of use of memory addressing modes (including immediates) .
These major addressing modes account for all but a few percent (0% to 3%) of the memory
accesses. Register modes, which are not counted, account for one-half of the operand refer-
ences, while memory addressing modes (including immediate) account for the other half. Of
course, the compiler affects what addressing modes are used; see Section A.8 . The memory
indirect mode on the VAX can use displacement, autoincrement, or autodecrement to form the
initial memory address; in these programs, almost all the memory indirect references use dis-
placement mode as the base. Displacement mode includes all displacement lengths (8, 16,
and 32 bits). The PC-relative addressing modes, used almost exclusively for branches, are
not included. Only the addressing modes with an average frequency of over 1% are shown.
As Figure A.7 shows, displacement and immediate addressing dominate addressing mode
usage. Let's look at some properties of these two heavily used modes.
Displacement Addressing Mode
The major question that arises for a displacement-style addressing mode is that of the range of
displacements used. Based on the use of various displacement sizes, a decision of what sizes to
support can be made. Choosing the displacement field sizes is important because they directly
affect the instruction length. Figure A.8 shows the measurements taken on the data access on
a load-store architecture using our benchmark programs. We look at branch offsets in Section
A.6 —data accessing paterns and branches are diferent; litle is gained by combining them,
although in practice the immediate sizes are made the same for simplicity.