Instruction Set Principles - Computer Architecture: A Quantitative Approach - page 496

Two major instruction set characteristics divide GPR architectures. Both characteristics con-
cern the nature of operands for a typical arithmetic or logical instruction (ALU instruction).
The first concerns whether an ALU instruction has two or three operands. In the three-oper-
and format, the instruction contains one result operand and two source operands. In the two-
operand format, one of the operands is both a source and a result for the operation. The second
distinction among GPR architectures concerns how many of the operands may be memory ad-
dresses in ALU instructions. The number of memory operands supported by a typical ALU
instruction may vary from none to three. Figure A.3 shows combinations of these two atrib-
utes with examples of computers. Although there are seven possible combinations, three serve
to classify nearly all existing computers. As we mentioned earlier, these three are load-store
(also called register-register), register-memory, and memory-memory.
FIGURE A.3 Typical combinations of memory operands and total operands per typical
ALU instruction with examples of computers . Computers with no memory reference per
ALU instruction are called load-store or register-register computers. Instructions with multiple
memory operands per typical ALU instruction are called register-memory or memory-memory,
according to whether they have one or more than one memory operand.
Figure A.4 shows the advantages and disadvantages of each of these alternatives. Of course,
these advantages and disadvantages are not absolutes: They are qualitative and their actual
impact depends on the compiler and implementation strategy. A GPR computer with
memory-memory operations could easily be ignored by the compiler and used as a load-store
computer. One of the most pervasive architectural impacts is on instruction encoding and the
number of instructions needed to perform a task. We see the impact of these architectural al-
ternatives on implementation approaches in Appendix C and Chapter 3 .