Fundamentals of Quantitative Design and Analysis - Computer Architecture: A Quantitative Approach - page 20

ally more important than performance for memory and disks, so capacity has improved most,
yet bandwidth advances of 300-1200X are still much greater than gains in latency of 6-8X.
Clearly, bandwidth has outpaced latency across these technologies and will likely continue
to do so. A simple rule of thumb is that bandwidth grows by at least the square of the im-
provement in latency. Computer designers should plan accordingly.
Scaling Of Transistor Performance And Wires
Integrated circuit processes are characterized by the feature size , which is the minimum size of
a transistor or a wire in either the x or y dimension. Feature sizes have decreased from 10 mi-
crons in 1971 to 0.032 microns in 2011; in fact, we have switched units, so production in 2011
is referred to as “32 nanometers,” and 22 nanometer chips are under way. Since the transist-
or count per square millimeter of silicon is determined by the surface area of a transistor, the
density of transistors increases quadratically with a linear decrease in feature size.
The increase in transistor performance, however, is more complex. As feature sizes shrink,
devices shrink quadratically in the horizontal dimension and also shrink in the vertical di-
mension. The shrink in the vertical dimension requires a reduction in operating voltage to
maintain correct operation and reliability of the transistors. This combination of scaling factors
leads to a complex interrelationship between transistor performance and process feature size.
To a first approximation, transistor performance improves linearly with decreasing feature
size.
The fact that transistor count improves quadratically with a linear improvement in tran-
sistor performance is both the challenge and the opportunity for which computer architects
were created! In the early days of microprocessors, the higher rate of improvement in density
was used to move quickly from 4-bit, to 8-bit, to 16-bit, to 32-bit, to 64-bit microprocessors.
More recently, density improvements have supported the introduction of multiple processors
per chip, wider SIMD units, and many of the innovations in speculative execution and caches
found in Chapters 2 , 3 , 4 , and 5 .
Although transistors generally improve in performance with decreased feature size, wires
in an integrated circuit do not. In particular, the signal delay for a wire increases in proportion
to the product of its resistance and capacitance. Of course, as feature size shrinks, wires get
shorter, but the resistance and capacitance per unit length get worse. This relationship is com-
plex, since both resistance and capacitance depend on detailed aspects of the process, the geo-
metry of a wire, the loading on a wire, and even the adjacency to other structures. There are
occasional process enhancements, such as the introduction of copper, which provide one-time
improvements in wire delay.
In general, however, wire delay scales poorly compared to transistor performance, creating
additional challenges for the designer. In the past few years, in addition to the power dissip-
ation limit, wire delay has become a major design limitation for large integrated circuits and
is often more critical than transistor switching delay. Larger and larger fractions of the clock
cycle have been consumed by the propagation delay of signals on wires, but power now plays
an even greater role than wire delay.
1.5 Trends in Power and Energy in Integrated Circuits
Today, power is the biggest challenge facing the computer designer for nearly every class
of computer. First, power must be brought in and distributed around the chip, and modern