Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 423

Data message contains the Ack count. Thus, the protocol assumes that the Data message is
processed before the Last Ack event.
5.13 [10/10/10/10/10/10] <5.4> Consider the advanced directory protocol described above and
the cache contents from Figure 5.38 . What is the sequence of transient states that the afec-
ted cache blocks move through in each of the following cases?
a. [10] <5.4> P0,0: read 100
b. [10] <5.4> P0,0: read 120
c. [10] <5.4> P0,0: write 120 <-- 80
d. [10] <5.4> P3,1: write 120 <-- 80
e. [10] <5.4> P1,0: read 110
f. [10] <5.4> P0,0: write 108 <-- 48
5.14 [15/15/15/15/15/15/15] <5.4> Consider the advanced directory protocol described above
and the cache contents from Figure 5.38 . What is the sequence of transient states that the
afected cache blocks move through in each of the following cases? In all cases, assume that
the processors issue their requests in the same cycle, but the directory orders the requests
in top-down order. Assume that the controllers' actions appear to be atomic (e.g., the dir-
ectory controller will perform all the actions required for the DS --> DM transition before
handling another request for the same block).
a. [15] <5.4> P0,0: read 120
P1,0: read 120
b. [15] <5.4> P0,0: read 120
P1,0: write 120 <-- 80
c. [15] <5.4> P0,0: write 120
P1,0: read 120
d. [15] <5.4> P0,0: write 120 <-- 80
P1,0: write 120 <-- 90
e. [15] <5.4> P0,0: replace 110
P1,0: read 110
f. [15] <5.4> P1,0: write 110 <-- 80
P0,0: replace 110
g. [15] <5.4> P1,0: read 110
P0,0: replace 110
5.15 [20/20/20/20/20] <5.4> For the multiprocessor illustrated in Figure 5.37 (with L2 caches
disabled) implementing the protocol described in Figure 5.39 and Figure 5.40 , assume the
following latencies:
■ CPU read and write hits generate no stall cycles.
■ Completing a miss (e.g., do Read and do Write) takes L ack cycles only if it is performed
in response to the Last Ack event (otherwise, it gets done while the data are copied to
cache).
■ A CPU read or write that generates a replacement event issues the corresponding
GetShared or GetModified message before the PutModified message (e.g., using a
write-back buffer).
■ A cache controller event that sends a request or acknowledgment message (e.g.,
GetShared) has latency L send_msg cycles.
■ A cache controller event that reads the cache and sends a data message has latency
L send_data cycles.