Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 385

FIGURE 5.22 State transition diagram for an individual cache block in a directory-
based system . Requests by the local processor are shown in black, and those from the home
directory are shown in gray. The states are identical to those in the snooping case, and the
transactions are very similar, with explicit invalidate and write-back requests replacing the
write misses that were formerly broadcast on the bus. As we did for the snooping controller,
we assume that an attempt to write a shared cache block is treated as a miss; in practice,
such a transaction can be treated as an ownership request or upgrade request and can deliv-
er ownership without requiring that the cache block be fetched.
The operation of the state transition diagram for a cache block in Figure 5.22 is essentially
the same as it is for the snooping case: The states are identical, and the stimulus is almost
identical. The write miss operation, which was broadcast on the bus (or other network) in the
snooping scheme, is replaced by the data fetch and invalidate operations that are selectively
sent by the directory controller. Like the snooping protocol, any cache block must be in the ex-
clusive state when it is writen, and any shared block must be up to date in memory. In many
multicore processors, the outermost level in the processor cache is shared among the cores (as
is the L3 in the Intel i7, the AMD Opteron, and the IBM Power7), and hardware at that level
maintains coherence among the private caches of each core on the same chip, using either an
internal directory or snooping. Thus, the on-chip multicore coherence mechanism can be used