Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 377

FIGURE 5.17 The data miss rates for the user and kernel components behave differ-
ently for increases in the L1 data cache size (on the left) versus increases in the L1
data cache block size (on the right) . Increasing the L1 data cache from 32 KB to 256 KB
(with a 32-byte block) causes the user miss rate to decrease proportionately more than the
kernel miss rate: the user-level miss rate drops by almost a factor of 3, while the kernel-level
miss rate drops only by a factor of 1.3. The miss rate for both user and kernel components
drops steadily as the L1 block size is increased (while keeping the L1 cache at 32 KB). In con-
trast to the effects of increasing the cache size, increasing the block size improves the kernel
miss rate more significantly (just under a factor of 4 for the kernel references when going from
16-byte to 128-byte blocks versus just under a factor of 3 for the user references).
Figure 5.18 shows the variation in the kernel misses versus increases in cache size and in
block size. The misses are broken into three classes: compulsory misses, coherence misses
(from both true and false sharing), and capacity/conflict misses (which include misses caused
by interference between the OS and the user process and between multiple user processes).
Figure 5.18 confirms that, for the kernel references, increasing the cache size reduces only the
uniprocessor capacity/conflict miss rate. In contrast, increasing the block size causes a reduc-
tion in the compulsory miss rate. The absence of large increases in the coherence miss rate
as block size is increased means that false sharing effects are probably insignificant, although
such misses may be ofseting some of the gains from reducing the true sharing misses.