Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 372

FIGURE 5.13 The contributing causes of memory access cycle shift as the cache size
is increased . The L3 cache is simulated as two-way set associative.
Increasing the cache size eliminates most of the uniprocessor misses while leaving the mul-
tiprocessor misses untouched. How does increasing the processor count affect different types
of misses? Figure 5.14 shows these data assuming a base configuration with a 2 MB, two-way
set associative L3 cache. As we might expect, the increase in the true sharing miss rate, which
is not compensated for by any decrease in the uniprocessor misses, leads to an overall increase
in the memory access cycles per instruction.